Verilog HDL高级数字设计

1 Introduction to Digital Design Methodology

1.1 Design Methodology-An Introduction

1.1.1 Design Specification

1.1.2 Design Partition

1.1.3 Design Entry

1.1.4 Simulation and Functional Verification

1.1.5 Design Integration and Verification

1.1.6 Presynthesis Sign-Off

1.1.7 Gate-Level Synthesis and Technology Mapping

1.1.8 Postsynthesis Design Validation

1.1.9 Postsynthesis Timing Verification

1.1.10 Test Generation and Fault Simulation

1.1.11 Placement and Routing

1.1.12 Physical and Electrical Design Rule Checks

1.1.13 Parasitic Extraction

1.1.14 Design Sign-Off

1.2 IC Technology Options

1.3 Overview

References

2 Review of Combinational Logic Design

2.1 Combinational Logic and Boolean Algebra

2.1.1 ASIC Library Cells

2.1.2 Boolean Algebra

2.1.3 DeMorgan s Laws

2.2 Theorems for Boolean Algebraic Minimization

2.3 Representation of Combinational Logic

2.3.1 Sum-of-Products Representation

2.3.2 Product-of-Sums Representation

2.4 Simplification of Boolean Expressions

2.4.1 Simplification with Exclusive-Or

2.4.2 Karnaugh Maps （SOP Form)

2.4.3 Karnaugh Maps （POS Form)

2.4.4 Karnaugh Maps and Don t-Cares

2.4.5 Extended Karnaugh Maps

2.5 Glitches and Hazards

2.5.1 Elimination of Static Hazards （SOP Form)

2.5.2 Summary: Elimination of Static Hazards in Two-Level Circuits

2.5.3 Static Hazards in Multilevel Circuits

2.5.4 Summary: Elimination of Static Hazards in Multilevel Circuits

2.5.5 Dynamic Hazards

2.6 Building Blocks for Logic Design

2.6.1 NAND-NOR Structures

2.6.2 Multiplexers

2.6.3 Demultiplexers

2.6.4 Encoders

2.6.5 Priority Encoder

2.6.6 Decoder

2.6.7 Priority Decoder

References

Problems

3 Fundamentals of Sequential Logic Design

3.1 Storage Elements

3.1.1 Latches

3.1.2 Transparent Latches

3.2 Flip-Flops

3.2.1 D-Type Flip-Flop

3.2.2 Master-Slave Flip-Flop

3.2.3 J-K Flip-Flops

3.2.4 T Flip-Flop

3.3 Busses and Three-State Devices

3.4 Design of Sequential Machines

3.5 State-Transition Graphs

3.6 Design Example: BCD to Excess-3 Code Converter

3.7 Serial-Line Code Converter for Data Transmission

3.7.1 Design Example: A Mealy-Type FSM for Serial Line-Code Conversion

3.7.2 Design Example: A Moore-Type FSM for Serial Line-Code Conversion

3.8 State Reduction and Equivalent States

References

Problems

4 Introduction to Logic Design with Verilog

4.1 Structural Models of Combinational Logic

4.1.1 Verilog Primitives and Design Encapsulation

4.1.2 Verilog Structural Models

4.1.3 Module Ports

4.1.4 Some Language Rules

4.1.5 Top-Down Design and Nested Modules

4.1.6 Design Hierarchy and Source-Code Organization

4.1.7 Vectors in Verilog

4.1.8 Structural Connectivity

4.2 Logic System, Design Verification, and Test Methodology

4.2.1 Four-Value Logic and Signal Resolution in Verilog

4.2.2 Test Methodology

4.2.3 Signal Generators for Testbenches

4.2.4 Event-Driven Simulation

4.2.5 Testbench Template

4.2.6 Sized Numbers

4.3 Propagation Delay

4.3.1 Inertial Delay

4.3.2 Transport Delay

4.4 Truth Table Models of Combinational and Sequential Logic with Verilog

References

Problems

5 Logic Design with Behavioral Models of Combinational and Sequential Logic

5.1 Behavioral Modeling

5.2 A Brief Look at Data Types for Behavioral Modeling

5.3 Boolean Equation-Based Behavioral Models of Combinational Logic

5.4 Propagation Delay and Continuous Assignments

5.5 Latches and Level-Sensitive Circuits in Verilog

5.6 Cyclic Behavioral Models of Flip-Flops and Latches

5.7 Cyclic Behavior and Edge Detection

5.8 A Comparison of Styles for Behavioral Modeling

5.8.1 Continuous Assignment Models

5.8.2 Dataflow/RTL Models

5.8.3 Algorithm-Based Models

5.8.4 Naming Conventions: A Matter of Style

5.8.5 Simulation with Behavioral Models

5.9 Behavioral Models of Multiplexers, Encoders, and Decoders

5.10 Dataflow Models of a Linear-Feedback Shift Register

5.11 Modeling Digital Machines with Repetitive Algorithms

5.11.1 Intellectual Property Reuse and Parameterized Models

5.11.2 Clock Generators

5.12 Machines with Multicycle Operations

5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy?

5.13.1 Tasks

5.13.2 Functions

5.14 Algorithmic State Machine Charts for Behavioral Modeling

5.15 ASMD Charts

5.16 Behavioral Models of Counters, Shift Registers, and Register Files

5.16.1 Counters

5.16.2 Shift Registers

5.16.3 Register Files and Arrays of Registers （Memories)

5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals

5.18 Design Example: Keypad Scanner and Encoder

References

Problems

6 Synthesis of Combinational and Sequential Logic

6.1 Introduction to Synthesis

6.1.1 Logic Synthesis

6.1.2 RTL Synthesis

6.1.3 High-Level Synthesis

6.2 Synthesis of Combinational Logic

6.2.1 Synthesis of Priority Structures

6.2.2 Exploiting Logical Don t-Care Conditions

6.2.3 ASIC Cells and Resource Sharing

6.3 Synthesis of Sequential Logic with Latches

6.3.1 Accidental Synthesis of Latches

6.3.2 Intentional Synthesis of Latches

6.4 Synthesis of Three-State Devices and Bus Interfaces

6.5 Synthesis of Sequential Logic with Flip-Flops

6.6 Synthesis of Explicit State Machines

6.6.1 Synthesis of a BCD-to-Excess-3 Code Converter

6.6.2 Design Example: Synthesis of a Mealy-Type NRZ-to-Manchester Line Code Converter

6.6.3 Design Example: Synthesis of a Moore-Type NRZ-to-Manchester Line Code Converter

6.6.4 Design Example: Synthesis of a Sequence Recognizer

6.7 Registered Logic

6.8 State Encoding

……

7 Design and Synthesis of Datapath Controllers

8 Programmable Logic and Storage Devices

9 Algorithms and Architectures for Digital Processors

10 Architectures for Arithmetic Processors

11 Postsynthesis Design Tasks

A Verilog Primitives

B Verilog Keywords

C Verilog Data Types

D Verilog Operators

E Verilog Language Formal Syntax

F Verilog Language Formal Syntax

G Additional Features of Verilog

H Flip-Flop and Latch Types

I Verilog-2001, 2005

J Programming Language Interface

K Web sites

L Web-Based Resources

Index

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