高速CMOS电路设计：Logical Effort方法

1TheMethodofLogicalEffort

1.1Introduction

1.2DelayinaLogicGate

1.3MultistageLogicNetworks

1.4ChoosingtheBestNumberofStages

1.5SummaryoftheMethod

1.6ALookAhead

1.7Exercises

2DesignExamples

2.1TheANDFunctionofEightInputs

2.2Decoder

2.3SynchronousArbitration

2.4Summary

2.5Exercises

3DerivingtheMethodofLogicalEffort

3.1ModelofaLogicGate

3.2DelayinaLogicGate

3.3MinimizingDelayalongaPath

3.4ChoosingtheLengthofaPath

3.5UsingtheWrongNumberofStages

3.6UsingtheWrongGateSize

3.7Summary

3.8Exercises

4CalculatingtheLogicalEffortofGates

4.1DefinitionsofLogicalEffort

4.2GroupingInputSignals

4.3CalculatingLogicalEffort

4,4AsymmetricLogicGates

4.5CatalogofLogicGates

4.6EstimatingParasiticDelay

4.7PropertiesofLogicalEffort

4.8Exercises

5CalibratingtheModel

5.1CalibrationTechnique

5.2DesigningTestCircuits

5.3OtherCharacterizationMethods

5.4CalibratingSpecialCircuitFamilies

5.5Summary

5.6Exercises

6AsymmetricLogicGates

6.1DesigningAsymmetricLogicGates

6.2ApplicationsofAsymmetricLogicGates

6.3Summary

6.4Exercises

7UnequalRisingandFallingDelays

7.1AnalyzingDelays

7.2CaseAnalysis

7.3OptimizingCMOSP/NRatios

7.4Summary

7.5Exercises

8CircuitFamilies

8.1Pseudo-NMOSCircuits

8.2DominoCircuits

8.3TransmissionGates

8.4Summary

8.5Exercises

9ForksofAmplifiers

9.1TheForkCircuitForm

9.2HowManyStagesShouldaForkUse?

9.3Summary

9.4Exercises

10BranchesandInterconnect

10.1CircuitsThatBranchataSingleInput

10.2BranchesafterLogic

10.3CircuitsThatBranchandRecombine

10.4Interconnect

10.5ADesignApproach

10.6Exercises

11WideStructures

11.1Ann-inputANDStructure

11.2Ann-inputMullerC-element

11.3Decoders

11.4Multiplexers

11.5Summary

11.6Exercises

12Conclusions

12.1TheTheoryofLogicalEffort

12.2InsightsfromLogicalEffort

12.3ADesignProcedure

12.4OtherApproachestoPathDesign

12.5ShortcomingsofLogicalEffort

12.6PartingWords

CastofCharacters

ReferenceProcessParameters

SolutionstoSelectedExercises

BIBLIOGRAPHY

INDEX

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