CMOS锁相环

"Preface

ListofAcronymsandSymbols

Introduction

1.1MOTIVATION

1.2SUMMARYOFBOOK

1.3BOOKORGANIZATION

REFERENCES

FrequencySynthesizerforWirelessApplications

2.1DEFINITIONANDCHARACTERISTICS

2.2PHASENOISEANDTIMINGJITTER

2.2.1Phasenoiseandspurioustone

2.2.2Timingjitter

2.3IMPLEMENTATIONOFFREQUENCYSYNTHESIZER

2.3.1Directanalogfrequencysynthesizer

2.3.2Directdigitalfrequencysynthesizer

2.3.3PLL-basedfrequencysynthesizer

2.3.4DLL-basedfrequencysynthesizer~...

2.3.5Hybridfrequencysynthesizer:.

2.3.6Summaryandcomparisonofsynthesizers

2.4FREQUENCYSYNTHESIZERFORWIRELESSTRANSCEIVERS

2.5OTHERAPPLICATIONSOFPLLANDFREQUENCYSYNTHESIZER

REFERENCES

PLLFrequencySynthesizer

3.1PLLFREQUENCYSYNTHESIZERBASICS

3.1.1Basicbuildingblocksofcharge-pumpPLL

3.1.2Continuous-timelinearphaseanalysis

3.1.3Lockingtime

3.1.4Trackingandacquisition

3.2FAST-LOCKINGTECHNIQUES

3.2.1Bandwidthgear-shifting

3.2.2VCOpre-tuning

3.3DISCRETE-TIMEANALYSISANDNONLINEARMODELING

3.3.1z-domaintransferfunctionandstabilityanalysis

3.3.2Nonlineardynamicbehaviormodeling

3.4DESIGNEXAMPLE:2.4GHZINTEGER-NPLLFORBLUETOOTH

REFERENCES

∑△FractionaI-NPLLSynthesizer

4.1∑△FRACTIONAL-NFREQUENCYSYNTHESIZER

4.1.1∑△quantizationnoisetophasenoisemapping

4.1.2∑△quantizationnoisetotimingjittermapping

4.2ACOMPARATIVESTUDYOFDIGITAL∑△MODULATORS

4.2.1Designconsiderations

4.2.2Fourtypesofdigital∑△modulators

4.2.3Summaryofcomparativestudy

4.3OTHERAPPLICATIONSOFEA-PLL

4.3.1Directdigitalmodulation

4.3.2Frequency-to-digitalconversion

4.4MODELINGANDSIMULATIONOF∑△-PLL

4.5DESIGNEXAMPLE:900MHz∑△-PLLFORGSM

REFERENCES5EnhancedPhaseSwitchingPrescaler

5.1PRESCALERARCHITECTURE

5.1.1Conventionalprescaler

5.1.2Phaseswitchingprescaler

5.1.3Injection-lockedprescaler

5.1.4Summaryandcomparisonofprescalers

5.2ENHANCEDPHASE-SWITCHINGPRESCALER

5.3CIRCUITDESIGNANDSIMULATIONRESULTS

5.3.1Eight45~-spacedphasesgeneration

5.3.28-to-1multiplexer

5.3.3Switchingcontrolcircuit

5.3.4Asynchronousfrequencydivider

5.4DELAYBUDGETINTHESWITCHINGCONTROLLOOP

5.5SPURSDUETONONIDEAL45PHASESPACING

REFERENCES

LoopFilterWithCapacitanceMultiplier

6.1LOOPFILTERARCHITECTURE

6.1.1Passiveloopfilter

6.1.2Dual-pathloopfilter

6.1.3Sample-resetloopfilter

6.1.4Otherloopfilterarchitectures

6.1.5Summaryandcomparisonofloopfilters

6.2LOOPFILTERANDCHARGE-PUMPNOISEMAPPING

6.3LOOPFILTERWITHCAPACITANCEMULTIPLIER

6.3.1Third-orderpassiveloopfilter

6.3.2Capacitancemultiplier

6.3.3Simulationofloopfilterwithcapacitancemultiplier

6.3.4Noiseconsideration

REFERENCES

OtherBuildingBlocksofPLL

7.1VCO

7.1.1LC-VCO

7.1.2Varactor

7.1.3Inductor

7.1.4VCOphasenoise

7.1.5Layout

7.2PHASE-FREQUENCYDETECTOR

7.3CHARGE-PUMP

7.3.1Referencespur

7.3.2Chargepumparchitectures

7.4PROGRAMMABLEDIVIDER

7.5DIGITALMODULATOR

7.6CHIPLAYOUT

REFERENCES

8PrototypeMeasurementResults

8.1PRESCALERMEASUREMENT

8.2LOOPFILTERMEASUREMENT

8.3PLLMEASUREMENT

REFERENCES

9ConclusionsAppendix

Index

"

　　本书国外电子信息精品著作(影印版)系列之一，是一本关于小型sigma-delta频率综合器方面的优秀著作，分别从系统级和电路级对频率综合器的设计进行了阐述。涉及PLL的基础问题，内容全面翔实，由浅入深，对PLL的关键问题提出了解决方案。　　本书是一本关于小型sigma-delta频率综合器方面的优秀著作。作者分别从系统级和电路级对频率综合器的设计进行了阐述。主要创新点在低功耗高速分频器和减少芯片面积的环路滤波器的电容设计上。该书涉及PLL的基础问题，内容全面翔实，由浅入深，对PLL的关键问题提出了解决方案。