宽带高动态范围DAC

"Preface

Glossary

Abbreviations

1DigitaltoAnalogconversionconcepts

1.1Functionalaspects

1.1.1DefinitionoftheD/Afunction

1.1.2Functionalspecifications

1.2Algorithmicaspects

1.3Signalprocessingaspects

1.3.1WaveformsandLinecoding

1.3.2SignalModulationconcepts

1.4Circuitaspects

1.4.1Architectureterminology

1.4.2Resistivevoltagedivisionarchitectures

1.4.3Capacitivevoltageandchargedivisionarchitectures

1.4.4Currentdivisionbasedarchitectures

1.5Conclusions

2FrameworkforAnalysisandSynthesisofDACs

2.1Overview

2.2Frameworkdescription

2.2.1Analysis

2.2.2Synthesis

3CurrentSteeringDACs

3.1Basiccircuit

3.1.1Partitioningandsegmentation

3.1.2Currentswitchingnetworkandcurrentsources

3.1.3Clock-datasynchronizationcircuit

3.1.4Auxiliarycircuits

3.2Implementationsandtechnologyimpact

4DynamiclimitationsofCurrentSteeringDACs

4.1Stateoftheartindynamiclinearity

4.2DynamiclimitationsofcurrentsteeringDACs

4.2.1Matchingandrelativeamplitudeprecision

4.2.2Matchingandrelativetimingprecision

4.3Conclusions

CurrentSteeringDACcircuiterroranalysis

5.IAmplitudedomainerrors

5.1.1Relativeamplitudeinaccuracies

5.1.2Outputresistancemodulation

5.2Timedomainerrors

5.2.1Nonlinearsettlingandoutputimpedancemodulation

5.2.2Asymmetricalswitching

5.2.3Modulationofswitchingbehavior

5.2.4Chargefeedthroughandinjection

5.2.5Relativetiminginaccuracies

5.2.6Powersupplybounceandsubstratenoise

5.2.7Clock(timing)jitter

5.3Conclusions

6High-levelmodelingofCurrentSteeringOACs

6.1Systemmodeling6.1.1Systemlayers

6.1.2Systemexcitationsandresponses

6.1.3Systemparameters

6.1.4Subsysteminteraction

6.1.5Systemmodulation

6.2Errorpropertiesandclassification

6.2.1Errorproperties

6.2.2Errorclassification

6.3Functionalerrorgenerationmechanisms

6.3.1Definitions

6.3.2Algorithmicmodeling

6.3.3Functionalmodeling

6.3.4Examples

6.4Conclusions

Functionalmodelingoftimingerrors

7,1Non-uniformtiming

7.1.1TheEquivalentTimingerrorofatransition

7.1.2Non-uniformtimingintheprocessofsignalsampling

7.1.3Non-uniformtimingintheprocessofsignalcreation

7.2Siocnasticnon-uniformtiminganaiysis

7.2.1Correlatednon-uniformtiming

7.2.2Whitenon-uniformtiming

7.2.3RZandNRZwaveforms

7.3Deterministicnon-uniformtiming

7.3.1Non-linearmappingoftimedomains

7.3.2Non-uniformtiminginsignalcreation

7.4Conclusions

Functionalanalysisoflocaltimingerrors

8.1Localtimingerroranalysis

8.1.1Equivalenttimingerrorcalculation

8.1.2Signalerrorcalculation

8.2Highlevelarchitecturalparametertradeoffs:segmentation

8.3Conclusions

Circuitanalysisoflocaltimingerrors

9.1Circuitanalysiswithlinearmodels

9.1.1Circuitbehavioral-levelanalysisoftimingerrorsinachain

9.1.2Transistorlevelanalysis

9.2Localtimingerrortradeoffs

9.2.1Switchtimingerrors

9.2.2Latchtimingerrors

9.3Conclusions

10SynthesisconceptsforCSDACs

10.1InformationmanagementintheCSDAC

10.1.1ThebasiccurrentsteeringDAChardware

10.1.2Informationsources

10.1.3Optionalhardware:detectionandcontroloperations

10.1,4Algorithms

10.1.5Space/Timeerrormappingandprocessing

10.2SynthesisPolicy

10.3A-posteriorierrorcorrectionmethods10.3.1Calibrationinamplitudeandtimedomain

10.3.2Generalizedmapping

10.3.3Applicationsofgeneralizedmapping

10.3.4Realizationissuesofthegeneralizedmappingconcept

10.4Conclusions

11Designofa12bit500Msample/sDAC

11.1Designapproach

11.2Architecture

11.2.1Signalingandcircuitlogic

11.2.2Powersupplyandbiasing

11.2.3Thermometer/binarybitspartitioning

11.3Switched-Currentcell

11.3.1Currentsource

11.3.2Switch

11.4Decoder,datasynchronizationandconditioning

11.4.1Binary-to-Thermometerdecoder

11.4.2Delayequalization

11.4.3Master-slavelatchesanddrivers

11.4.4Clockbuffer

11.5Layout

11.6Experimentalresults

11.6.1DClinearitymeasurements

11.6.2AClinearitymeasurements

11.7Conclusions

References

AOutputspectrumfortimingerrors

A.1Powerspectrumofy(t)forrandomtimingerrors

A.2Spectrumofy(t)fordeterministictimingerrors

BLiteraturedata

"

　　本书是国外电子信息精品著作。宽带高动态范围DAC是现代信息系统的基本构件，本书的亮点在于提出了详细的方案，可以解决由失配和时钟串扰引起的时序误差，实现了12位、采样率500M、0.18um工艺的高性能DAC。本书独辟蹊径，建立了超越电流舵结构的分析和综合方法。　　宽带高动态范围DAC是现代信息系统的基本构件。目前的电流舵DAC具有在较宽的频率范围内取得高动态性能的潜力。然而，它们在更高频率时的性能被非线性限制了。宽带高动态范围DAC是解决这一缺陷的有效方法。本书的亮点在于提出了详细的方案，可以解决由失配和时钟串扰引起的时序误差，实现了12位、采样率500M、0.18um工艺的高性能DAC。本书独辟蹊径，建立了超越电流舵结构的分析和综合方法。