时钟发生器在片上系统处理器中的应用

ABOUTTHEAUTHOR

PREFACE

FOREWORD

1.INTRODUCTION

1.1WHATARESYSTEM-ON-A-CHIPPROCESSORS?

1.2ORGANIZATION

2.PHASE-LOCKEDLOOPFUNDAMENTALS

2.1Introduction

2.2PLLBasics

2.2.1PLLSpecifications

2.2.2ChargePumpPLLs

2.2.3PLLBuildingBlocks

2.3Continuoas-timeLinearAnalysisofPLLs

2.4Discrete-timeLinearAnalysisofPLLs

2.5NonlinearLockingBehaviourofPLLs

2.6Summary

3.LOW-VOLTAGEANALOGCMOSDESIGN

3.1Introduction

3.2MOSTransistors

3.3Low-VoltageCurrentMirrors

3.4Low-VoltageChargePumps

3.5Low-VoltageOscillatorDesign

3.5.1DigitalTuningCircuitry

3.5.2RingOscillatorDesign

3.5.3LCVCODesign

3.6VoltageandCurrentReferences

3.7Summary

4.JITTERANALYSISINPHASE-LOCKEDLOOPS

4.1Introduction

4.2JitterBasics

4.2.1DefinitionofJitter

4.2.2SourcesofJitter

4.2.3JitterandPhaseNoise

4.3JitterinVoltageControlledOscillators

4.3.1ClassicalPhaseNoiseAnalysis

4.3.2CyclostationaryPhaseNoiseAnalysis

4.3.3CMOSVoltageControlledRingOscillators

4.3.4JitterinDifferentialLCVCOs

4.4JitterPerformanceofClosed-LoopPLLSystem

4.4.1BasicLinearAnalysis

4.4.2EffectofVaryingLoopParameters

4.4.3EffectofPFDNonlinearitiesonJitter

4.5CouplingNoiseEffectsonJitter

4.5.1PowerSupplyCouplingNoise

4.5.2SubstrateCouplingNoise

4.6Summary

5.LOW-JITTERPLLARCHITECTURES

5.1Introduction

5.2DifferentialPLLArchitecture.

5.2.1ConventionalTopology

5.2.2Low-NoiseDifferentialPLLTopology

5.3SupplyVoltageRegulatedPLLArchitectures

5.3.1BasicConcept

5.3.2RegulatorTopologies

5.3.2.1LinearVoltageRegulator

5.3.2.2SourceFollowerVoltageRegulator

5.3.2.3HybridVoltageRegulationApproach

5.3.3PerformanceComparison

5.4AdaptivePLLArchitectures

5.4.1Two-ModeBandwidthArchitecture

5.4.2ProcessInsensitiveDesign

5.4.3AnalogLoopBandwidthController

5.5ResistorlessLoopFilterPLLs

5.5.1BasicConcept

5.5.2Sample-ResetLoopFilter

5.6Delay-LockedLoopFrequencyMultipliers

5.6,1DLLOperatingPrinciple

5.6.2DLLasaFrequencySynthesizer

5.6.3JitterAnalysis

5.6.4HybridPLL/DLLApproach

5.7Summary

6.DIGITALPLLDESIGN

6.1Introduction

6.2BasicTopology

6.3Z-domainAnalysis

6.3.1LinearModelofDPLL

6.3.2LinearPerformanceEvaluation

6.4CircuitImplementationIssues

6.4.1DACoptimization

6.4.2Referencecurrenttemperaturestability

6.4.3ExperimentalResults

6.5AlternateDigitalPLLforClockGeneration

6.5.1All-DigitalPLLforDigitallyControlledOscillator

6.5.2All-DigitalFLLwithPhaseReset

6.6Summary

7.DSPCLOCKGENERATORARCHITECTURES

7.1Introduction

7.1.1Whyimportant?

7.1.2TypicalDSPClockGenerationSpecifications

7.2SamplingClockRequirementsforDataConverters

7.2.1FirstorderAnalysis

7.2.2GeneralCase-AQualitativeApproach

7.2.3GeneralCase-AQuantitativeApproach

7.2.4SpecificCase-Sigma-DeltaA/DConverters

7.3JitterinFrequencyDividers

7.3.1UsesofFrequencyDividersinSoCProcessors

7.3.2MechanismofJitterindigitalfrequencydividers

7.3.3SynchronousDividerModel

7.3.4AsynchronousDividerModel

7.3.5Results

7.4Fractional-NPLLsasClockGenerators

7.4.1BasicToplogy

7.4.2Sigma-DeltaPLLs

7.4.2.1BasicOperation

7.4.2.2Sigma-DeltaDithering

7.5OversampledPLLTopologies

7.6DirectDigitalSynthesiswithAnalogInterpolation

7.6.1MNAConceptandArchitecture

7.6.2ParameterAnalysisofMNACounter

7.6.3CircuitImplementation

7.6.4Results

7.7Summary

8.DESIGNFORTESTABILITYINPLLS

8.1Introduction

8.2VerificationofSoCPLLs

8.2.1Overview

8.2.2RequiredPLLTests

8.3JitterMeasurementTechniques

8.3.1High-BandwidthATEJitterMeasurementSetup

8.3.2ATEJitterTestEquipment

8.4DesignforTestabilityandSelf-TestinPLLs

8.4.1FunctionalTest

8.4.2IndirectJitterMeasurementTechniques

8.4.3PreciseOn-ChipJitterMeasurement

8.5Summary

9.CLOCKPARTITIONINGANDSKEWCONTROL

9.1Introduction

9.2ClockDistributionNetworksinSoCs

9.3PerformanceLimitationsinClockNetworks

9.4ActiveSkewManagementStrategies

9.4.1EffectofClockSkew,JitteronPowerConsumption

9.4.2Ad-hocDeskewStrategies

9.4.3DLL-basedDeskewStrategies

9.5Multi-phaseClockGenerator

9.5.1PassiveMethod

9.5.2Master-SlaveDLL

9.5.3PulsewidthControlLoops

9.6Low-PowerClockDistributionStrategies

9.6.1ActiveClockGating

9.6.2Low-PowerGigahertzClockStrategies

9.7Multi-clockDomainInterfacing

9.8Summary

INDEX

　　本书针对在SOC芯片上使用的全集成频率合成器的设计，从电路和系统的角度对锁相环的原理和设计进行了分析。特别是在电路层次上，讨论了深亚微米CMOS数字工艺中的低电压模拟电路的设计，有比较大的参考意义。在对锁相环基本工作原理分析的基础之上，本书分析了具体的时钟产生方案和电路设计问题，并进一步讨论了锁相环的应用。　　本书针对在SOC芯片上使用的全集成频率合成器的设计，从电路和系统的角度对锁相环的原理和设计进行了分析。特别是在电路层次上，讨论了深亚微米CMOS数字工艺中的低电压模拟电路的设计，有比较大的参考意义。在对锁相环基本工作原理分析的基础之上，本书分析了具体的时钟产生方案和电路设计问题，并进一步讨论了锁相环的应用。本书还包括了PLL可测试性设计的内容。最后还从宏观角度讨论了SOC时钟域的设计。书中包含的大量实际问题分析应该有助于读者更好地理解时钟产生器设计中的核心问题。